1. Field of the Invention
The present invention relates to an improvement of a logic circuit which utilizes a field effect transistor.
2. Description of the Related Art
Various types of semiconductor logic circuits exist, and in many cases, these logic circuits are formed as an integrated circuit. Further, when a logic circuit is formed by unit logic circuits, the power dissipation of the logic circuit should be low (i.e., low power supply voltage), and the number of power sources for supplying the power should be kept as small as possible to improve the suitability of these unit logic circuits for the above integrated circuit. Further, it is required that the unit logic circuit have only a small delay, operate at a high speed, provide a high load driving ability, provide a high logic function, and provide a high margin.
A conventional circuit is formed by depletion type field effect transistors (hereinafter called D-FET transistor), and therefore, two power sources are required, and a level shift is required for the source follower circuit. Further, the power dissipation is high, the output logic function is low, and the load driving ability is not satisfactory.